Aligners have been used when terminating a synchronous multiplex. such as a framed 2048 kbit/s link, onto a clocked functional unit, where the clock of the functional unit and the synchronous multiplex cannot be assumed to be of the same frequency and phase.
The use of aligners implies a synchronous service which will tolerate (although reluctantly) some slips. The design characteristic of an aligner is that if the limit of its buffering is reached then a controlled slip is performed. Aligners not only must be able to accept any phase of the incoming stream, but also must include sufficient hysteresis to cope with delay variations introduced by the network.
The use of aligners can also be extended to data carried by a cell based Asynchronous Transfer Mode (ATM) Virtual, Channel, so that traffic of a nominal constant bit rate can be transferred from an ATM multiplex onto functional units which are expecting traffic of the same nominal constant bit rate. Such a clocked functional unit could be a synchronous switch or a digital to analogue to decoder.
Asynchronous traffic is characterised by being carried in packets, frames or cells, cells being the term commonly used for ATM traffic. ATM cells are of a constant size and can carry a fixed amount of constant bit rate traffic data.
When an aligner slips it must miss out a fixed amount of data if the traffic is arriving too quickly. If the traffic is arriving too slowly, then either a fixed amount of data is repeated or a fixed substitution set of data is inserted.
A Virtual Channel ATM cell aligner described is suitable for cell streams where the cell delay variation is not greater than the average cell arrival rate of the cell stream. Consequently cell aligners are appropriate for low bit rate circuits such as 64 kbit/s.
According to the present invention there is provided a method of terminating an Asynchronous Transfer Mode (ATM) multiplexed data stream at a depacketising functional unit, where virtual channel data not including a frame alignment signal is carried in cells in the data stream, each of the cells having a message sequence number, the method comprising aligning the cells using a plurality of cell buffers each storing the payload data contained in a single cell, the cell buffers being sequentially identified in accordance with the lower significant bits of the message sequence number, conditionally loading an appropriately identified cell buffer with each cell from the data stream in accordance with the lower significant bits of the message sequence number provided the message sequence number does not correspond to the message sequence number of the cell buffer currently being depacketised and is not more than a pre-determined number M of message sequence numbers in advance of the cell buffer being depacketised or an empty cell buffer being replaced by a fill-in cell; and emptying the cell buffers according to the conditions of a combined depacketiser and slip algorithm to form a continuous data stream aligned to the clock and frame start signal of the depacketising functional unit; on the failure of a valid cell to arrive replacing the missing cell by a fill-in cell in the continuous data stream by means of a fill-in cell format generator; and employing a time-out function which is cleared and restarted after each valid cell is received in order to cause a restart of the combined depacketiser and slip algorithm if the time-out should mature.
Electronics and Communications in Japan; Part I Commnunications; 76 (1993) December, No. 12, New York, US pp 14-26 xe2x80x9cCell Delay Variation Smoothing Methods for ATM based SDH Signal Transport System Hitoshi Uematsu and Hironi Ueda describes where if the synchronous digital hierarchy (SDH) signal is converted into asynchronous transfer mode (ATM) cells to be transmitted through the ATM transport network, the efficiency of the operation/management/maintenance of the network will be improved in addition to maintaining the economy and reliability of the network. This is one of the advantages of the ATM transport network.
There is further considered the system where SDH signal is transported by ATM technique. The delay variation produced in the ATM transport network is evaluated. Then the buffer read-out control and the required buffer capacity are discussed. The order of processing between the delay variation smoothing function and other required functions in the proposed system is analysed.
The depacketiser contains sufficient cell buffers to handle the expected delay variation, 2 cell buffers for less than 2 millisecond and 4 cell buffers for up to 6 milliseconds of delay variation.
When a cell is loaded into a cell buffer within the depacketiser, a full/empty binary flag is set to full and the time-out is cleared and re-started. When a cell buffer has just finished being emptied, its full/empty binary flag is set to empty.
There is further provided a method of aligning one ATM Virtual Channel cell stream, of an ATM multiplex which includes a depacketiser wherein the combined depacketiser and slip algorithm is defined as: if on two successive occasions during the depacketisation of cell (n), or the generation of a fill-in cell to replace cell (n), the arrival of cell (n+M) occurs before B bytes of cell (n) have been depacketised, then the first S bytes of the next cell to be depacketised, or replaced by a fill-in cell, are discarded in order to introduce a forward slip of S bytes; otherwise if after the completion of the depacketisation of cell (n) or the generation of a fill-in cell to replace a missing cell (n), cell (n+1) has been received then cell (n+1) is fully depacketised and becomes the new cell (n); or if after the completion of the depacketisation of cell (n) or the generation of a fill-in cell to replace a missing cell (n), cell (n+1) has not been received then cell (n+1) is replaced by a fill-in cell and becomes the new cell (n); unless if within S byte periods of the starting of a fill-in cell to replace cell (n), the missing cell (n) is received, then a backward slip of S bytes is achieved by halting the fill-in cell after S bytes and depacketising the received cell (n).
When M=3. B=47 bytes and S=47 bytes;
When M=2. B=47 bytes and S=23 bytes;
When M=1. B=15 bytes and S=16 bytes.